Advancements in technology in the semiconductor industry have created a need for very high pin count packages. Traditionally, semiconductor packages were wire bonded from a semiconductor die to a package substrate wherein the final package substrate had external electrical contacts which could be accessed by users. As designs have become more complex, the need for more Inputs and Outputs (I/O) has surpassed the ability to provide the additional I/O by conventional wire bond methods. Therefore, advanced packaging techniques, such as direct die attach, have been developed. With direct die attach techniques, such as flip chip, the die is attached directly to the packaged substrate which in turn provides the necessary electrical traces to the external contacts to the device.
One high I/O package is a Ball Grid Array package (BGA). A BGA package when viewed from the underside has a full or partial array of solder balls attached. The BGA package in turn can be attached to a printed circuit board by an end user. While the array structure of the BGA package allows for a high number I/O, there are problematic issues associated with routing the trace signals from the bonding fingers which attach to the die. One method of overcoming the routing problem associated with die bonding large I/O packages to BGAs has been to use the direct die attach packages previously discussed. By eliminating the space used by the wire bonding posts or fingers and the wire bonds themselves, additional routing space can be obtained allowing greater optimization during routing. However, the use of direct die attached technology can be expensive. For example, depending upon the size of a die, the use of a C-4 process in manufacturing a semiconductor device can result in a die cost in excess of five times greater than the die cost associated with a traditional wire bonded semiconductor die.
Another solution to improve routability is to add additional routing layers to the package. However, adding additional routing layers to the package increases the overall cost of the package. Therefore, one of the problems associated with high pin count packages are the additional costs that can be required either in the package device design, or the semiconductor device design.
Another problem associated with the use of BGA packages is that during the packaging process, it is necessary to plate the solder pads and/or the bond posts using an electrolysis method. Generally, Nickel/Gold is used in this electroplating process to provide a wire bondable surface and to protect the solder pads from atmospheric corrosion. The process of electrolytically plating the solder pads requires an electrical connection to each one of the solder pads of the BGA package. As a result, it is necessary to form an electrical connection from each wire bond post and BGA solder pad to an external electroplating bus. The need for this electroplating connection requires additional routing, including plating traces, from the bond fingers, vias, or the solder pads associated with the package. In the prior art, the top and bottom layer of the BGA package have plating busses for making electrical contact to each solder pad during electroplating. Generally, the plating busses run the entire periphery of the device being processed. Plating traces are connected to one of the plating busses in order to create the contact needed.
By making an electrical connection to the plating bus, each of the wire bond post and BGA package solder balls can be electrically contacted thereby allowing the electroplating process. However, availability of routing space for the functional traces is further limited by the need for electroplating traces, especially, where large pin counts, large die, and the need for smaller substrates exists. In addition, the problem of routing the plating traces needed to allow for electroplating is made more difficult based upon pin to ball assignments which can be specified by the designers of the semiconductor devices. Therefore, a new routing scheme which does not require additional cost to the packaging, and allows for more efficient routing of the plating traces would be desirable.